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features ? wide output voltage range: 6v to 500v ? low input voltage: 2.7v ? 5w maximum output power with external mosfet driver ? maximum output current: 100ma ? built-in charge pump converter for the gate driver ? programmable switching frequency from 40 khz to 400khz ? four programmable duty cycles from 50% to 87.5% ? fb return ground switch for power savings applications ? built-in delay timer for internal protection ? non-isolated dc/dc converter ? processed with hvcmos ? technology applications ? portable electronic equipment ? mems ? printers general description the hv9150 is a high output voltage hysteretic mode step up dc/dc controller that has both a built-in charge pump converter and a linear regulator for a wide range of input voltage. the charge pump converter mode is ideal for battery powered applications. the internal converter can provide a minimum of 5.0v gate driver output voltage (at v in = 2.7v) to the external n-channel mosfet. the range of 2.7v to 4.5v input supply voltage is ideal for battery powered applications such as portable electronics equipment. the internal linear regulator is selected when a higher supply voltage rail is available in the system. a feedback return ground path switch is also integrated in the device to minimize the quiescent current during the controller shutdown. this feature provides power savings for energy critical applications. in addition, a built-in timer is available to protect the internal circuit and to help dissipate the energy from the external high voltage storage capacitor. this device is designed for systems requiring high voltage and low current applications such as mems devices. block diagram high voltage output hysteretic mode step up dc/dc controller ccp2 r freq v out 6.0 - 500v v in 2.7 - 4.5v gnd r 1 r 2 l ct ccp1 vdd vll cp_en ga te ext_ref fb_rtn fb en freq_adj vcontrol 0v/3.3v hv9150 supertex inc. hv9150 supertex inc. www .supertex.com doc.# dsfp-hv9150 nr120213
2 absolute maximum ratings* * all voltages referenced to device gnd. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifcations is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter value v ll , input voltage supply -0.5v to 5.0v v dd , charge pump output voltage -0.5v to 13.6v logic input levels -0.5v to v ll +0.5v continuous power dissipation (note: on a 3 by 4 fr4 pcb @t a = 25c) 3000mw maximum junction temperature +125c operating temperature range -40c to +85c storage temperature range -65c to +150c ordering information part number package option packing HV9150K6-G 16-lead (3x3) qfn 3000/reel pin confguration product marking 16-lead qfn 16-lead qfn (top view) package may or may not include the following marks: si or typical thermal resistance package ja 16-lead qfn 33c/w xff icvg hdatvp hd xeqpvtqn" htgsacfl gzvatgh ev xnn ipf gp eragp eer3/ eer3- eer4/ eer4- 1 16 h150 ywll y = last digit of year sealed w = code for week sealed l = lot number = ?green? packaging symbol parameter min typ max units conditions v ll input voltage (cp mode) 2.7 - 4.5 v --- v ih high-level input voltage 0.8v ll - v ll v --- v il low-level input voltage 0 - 0.2v ll v --- t j junction temperature range -25 - 125 c --- recommended operating conditions power-up and power-down sequence power-up sequence should be the following: 1. connect ground. 2. apply v in . 3. set all inputs to a known state. power-down sequence should be the reverse of the above. -g denotes a lead (pb)-free / rohs compliant package note: pads are at the bottom of the package. center heat slug is at ground potential. hv9150 supertex inc. www .supertex.com doc.# dsfp-hv9150 nr120213
3 sym description min typ max unit conditions power supply i llq(off) quiescent v ll supply current (en = 0) - - 2.0 a --- i ll(on) v ll supply current (en = 1) gate = nc - - 1.5 ma f osc = 100khz, v ll = 4.5v gate = 300pf - - 4.0 i dd(on) v dd supply current (en = 1) gate = nc - - 1.0 ma f osc = 100khz, v dd = 12.6v gate = 300pf - - 2.5 i ddq(off) quiescent v dd supply current (en = 0) - - 2.0 a --- i ih high-level logic input current - - 1.0 a v ih = v ll i il low-level logic input current - - -1.0 a v il = 0v gate gate driver output voltage v ll = 4.5v gate = nc 10.2 - 12.3 v --- v ll = 2.7v gate = nc 5.0 - 6.9 v ll(ldo) linear regulator output voltage 3.0 - 3.6 v --- ac electrical characteristics (over recommended operating supply voltages and temperatures unless otherwise noted) sym description min typ max unit conditions feedback (fb) v ref internal feedback reference voltage accuracy 1.22 1.25 1.28 v --- range 1.20 1.25 1.30 t j = -25 to 85c i bias input bias current - - 1.0 a ext_ref is selected ext_ref external reference voltage range 0 - v ll -1.4 v --- trigger int reference 0 - 0.12 v during en positive triggering trigger ext reference 0.5 - v ll -1.4 v fb_rtn on-resistance, r ds - - 500 i o = 2.0ma breakdown voltage, bv - - 13.5 v --- gate driver output (gate) t r rise time - - 36 ns c l = 300pf, v dd = 12v t f fall time - - 12 ns r up pull up resistance v dd = 5.0v - - 45 i o = 50ma v dd = 12v - - 30 r down pull down resistance v dd = 5.0v - - 15 v dd = 12v - - 12 dc electrical characteristics (over recommended operating supply voltages and temperatures unless otherwise not ed) hv9150 supertex inc. www .supertex.com doc.# dsfp-hv9150 nr120213
4 sym description min typ max unit conditions f gate oscillator frequency - ? f osc - khz --- charge pump converter v dd charge pump output voltage 5.0 3v ll -1.8 12.6 v 2.7v v ll 4.5v c cp1 = 220nf c cp2 = 220nf c cp3 = 220nf f osc oscillator frequency accuracy 170 195 220 khz r freq = 270k, v ll = 3.3v range 40 - 400 over r freq range f oscillator frequency tolerance - 15 - % 50khz f osc 250khz dc duty cycle accuracy 86 87.5 89 % r freq = 270k range - 0 - % 0< v cntl 0.18v ll - 50 - % 0.22v ll < v cntl 0.38v ll - 62.5 - % 0.42v ll < v cntl 0.58v ll - 75 - % 0.62v ll < v cntl 0.78v ll - 87.5 - % 0.82v ll < v cntl v ll v control duty cycle adjustment 0 - v ll v see table r freq frequency adjustment resistor 120k - 1.2m --- r cp maximum charge pump output resistance pull up - - 20 v ll = 2.7v, i o = 10ma pull down - - 20 v ripple output ripple at v dd - - 100 mv 2.7v v ll 4.5v f osc = 200khz c cp1 = 220nf c cp2 = 220nf c cp3 = 220nf c gate = 300pf bw = 20mhz delay timer t delay shutdown delay timer - 240 - ms c t = 1.0f ac electrical characteristics (over recommended operating supply voltages and temperatures unless otherwise noted) hv9150 supertex inc. www .supertex.com doc.# dsfp-hv9150 nr120213
5 functional block diagram delay osc 3x charge pump converter ldo vref - + hysteretic mode controller v dd v dd v ll v ll v ll v ll ccp1+/- ccp2+/- vdd vll gnd ct en freq_adj vcontrol (duty cycle adj) cp_en ga te ext_ref fp_rtn fb ldo mode cp mode functional description hysteretic mode controller a hysteretic mode controller consists of an oscillator, a voltage reference, a comparator and a driver. both the internal oscillator and the duty cycle of the gate driver are running at a fxed rate. as this device is designed for a step up conversion, a pulse train is used to control the switch of a classical switching boost converter. the pulse train is gated by the output of the comparator, which compares the feedback of the output voltage with the voltage reference. if the output voltage reaches the target voltage, the comparator will turn off the pulse train. when the output voltage drops below the target voltage, the comparator will pass the pulse train to the switch and start the inductor charging cycle. the advantage of this hysteretic mode controller is its stability and simple operation. hysteretic mode controller and a classical boost converter internal oscillator this device has an internal oscillator which generates the reference clock for the hysteretic mode controller. the controller is running at half of the frequency of the internal oscillator. this oscillator is powered by the vll power supply pin. xqwv xkp j{uvgtgvke"oqfg eqpvtqnngt hv9150 supertex inc. www .supertex.com doc.# dsfp-hv9150 nr120213
6 the frequency of the oscillator is set by the external resistor r freq , and this frequency is inversely proportional to the value of r freq . its characteristic is shown in the f osc vs r freq diagram. f osc = 1 4 ? r freq ? c where c = 4.75pf voltage reference (vref) the voltage reference is used by the comparator to compare with the feedback voltage and the boost converter output. this device provides the options of using either its internal voltage reference or an external voltage reference. the internal voltage reference provides a stable 1.25v with a tolerance of 2.5%. with the use of 1% tolerance feedback resistors, the output can be achieved with a tolerance of 4.5%. in order to use the internal voltage reference, the ext_ref pin must be connected to ground. if the output voltage of the boost converter is required to have high precision and tight tolerance, the external voltage reference can be used to achieve that purpose. the external reference voltage must be between 0.5v and v ll -1.4v, and connect to the ext_ref pin. a single low to high transition must be presented at the en pin to trigger the device to select an external voltage reference. if no enable control signal is available in the application, this signal can be easily mimicked by a simple rc circuit. voltage connection reference gate driver (gate) the mosfet gate driver of this controller is specially designed to be able to drive the gate of the external mosfet up to 12v. a high pulse voltage will help to minimize the on-resistance of the external mosfet transistor. a lower on-resistance improves the overall effciency and heat dissipation. this gate driver is powered by the supply voltage v dd which can be generated by either the internal charge pump converter (cp mode) or the external power supply (ldo mode), depending on the available voltage supply rail of the application. charge pump converter (cp mode) a 3x charge pump converter is integrated into this device to provide a 5v to 12v rail for the gate driver. it can be activated by setting cp_en to ground. a 3.3v supply is more common and easily available for digital logic systems; however, this voltage level is less desirable for driving a high voltage mosfet to obtain a lower on-resistance for better effciency. in order to reduce the number of supply rails used in the system, an internal two stage charge pump converter is added, which can boost the 3.3v supply voltage to 8.0v. a 8.0v gate driver output will outperform a 3.3v gate driver by far and substantially improves the on-resistance of the external mosfet. the charge pump input can operate with an input voltage from 2.7v to 4.5v. its input and output are connected to the vll and vdd pins, respectively. three times (3x) charge pump converter linear regulator (ldo mode) in some applications, effciency may be a key factor, and higher voltage rails such as 5v, 6v, 9v or 12v may be available in the system. the internal charge pump converter cannot operate with these voltage levels because of the maximum output voltage limit of the charge pump converter. at the same time, these voltage levels are high enough to provide an adequate supply for the gate driver. under this circumstance, an internal linear regulator is used to replace the charge pump converter. this linear regulator input can accept voltage from 5.0v to 12.0v, and generates a 3.3v output to supply to the internal circuit. this linear regulator can be activated by setting cp_en to vll. in a scenario when the device is operating in ldo mode and in shutdown state (en = 0), the voltage at vll is undefned. in order to wake up the controller device, a voltage above 2.7v has to be presented at the enable pin (en). fb ground return switch (fb_rtn) any dc/dc controller requires a feedback from the output to monitor its operation so that it can regulate its output accordingly. a simple resistor network is used in conjunction with a feedback ground switch as a feedback path. the purpose of this feedback ground switch is to save power consumed by the feedback resistor network when the controller is disabled. this function is quite useful for power saving especially for battery operated applications. xff xnn que gnd vin ext_ref ext_ref gnd vo ltage referenc e internal external hv9150 supertex inc. www .supertex.com doc.# dsfp-hv9150 nr120213
7 shutdown timer and timing capacitor (c t ) a shutdown timer is also integrated into the controller for safety purposes. when the controller shuts down from its normal operation, the converter initial output is still at its high level. if the feedback ground return switch is disabled at the same time, a current path is created from the output via the feedback resistor, and the internal protection clamping diode at the fb pin. depending upon the value of the fb resistor, this momentarily conducting current can be high enough to damage this clamping diode. in order to avoid this potential problem, a timer is added to the disable function to keep the feedback ground switch to the on position for a short period of time. this on time duration is controlled by an external capacitor c t . the larger the capacitor value is, the longer this on time is. its characteristic is shown in the performance section. internal protection diode at fb pin hysteretic controller enable (en) the controller enable pin (en), serves two main purposes. the most obvious function is to turn the controller on and off, and the other function is to act as a trigger to activate the device to accept external voltage reference. for any applications required a highly precise voltage reference, an external voltage reference should be used. to activate the device to accept the external voltage reference, a low to high transition has to appear at the en pin while the voltage at the ext_ref pin is above 0.5v. if the system lacks enable function control, a rc circuit can be used to mimic this function to allow the external voltage reference. simple rc circuit for en pin duty cycle control (vcontrol) the input voltage at the vcontrol pin controls the duty cycle of the internal oscillator output to the gate driver. the internal comparators are all powered by the v ll supply and their input threshold voltages are all referenced to v ll volt- age. a voltage divider formed by the two resistors can be adjusted accordingly to select the desired duty cycle of the pulse signal to the gate driver. please see the table below. vcontrol duty cycle 0 to 0.18v ll 0% 0.22 to 0.38v ll 50% 0.42 to 0.58v ll 62.5% 0.62 to 0.78v ll 75% 0.82 to 1.0v ll 87.5% vout 0v/3.3v delay ct gnd fb_rtn fb en r 2 r 1 internal protection diode gnd en 3.3v (min) r c + - + - + - + - duty cycle 87.5 % v control v ll v ll duty cycle 75.0 % duty cycle 62.5 % duty cycle 50.0 % hv9150 supertex inc. www .supertex.com doc.# dsfp-hv9150 nr120213
8 design procedure there are several parameters that a user will decide for the dc/dc converter design. the input voltage, output voltage and output power requirement are usually defned at the beginning. the few parameters that the user needs to decide on include: operating frequency, inductor value, duty cycle and the on-resistance of the mosfet. there is some degree of fexibility in deciding the values of these parameters. the following provides the user a general approach to this subject. step 1 since this dc/dc controller device is operating in a discontinuous conduction mode, the following equations are used to determine the inductance and the switching frequency. given: d = duty cycle r = load resistance of the high voltage output v i = minimum input voltage v o = output voltage unknown: l = inductance f gate = driver switching frequency where: k = 2 ? l ? f gate r the maximum duty cycle can be determined by the following equation: d max = 1 - v i v o then, the user can choose any duty cycle less than d max . it is recommended that the largest possible setting be chosen. to compensate for the limited effciency, the user can add the effciency factor into the load resistance r. with the above equation, the product of l and f gate is determined. the design will be limited by the product of l and f gate . step 2 the standard inductor is usually sold in an incremental inductance value, for example, 10, 22, 33 or 47 h. the user can choose the inductance based on the size of the inductor, the peak current, the maximum operating frequency and the dc resistance. after the value of l is decided, the gate driver switching frequency can be computed. the required r freq resistance can be found in the f gate vs r freq table. next, the peak current of the inductor is checked by the following equation. the saturation current of the inductor must be larger than i peak . i peak = v i ? d l ? f gate step 3 the most important factors to determine the mosfet are the breakdown voltage, the current capability, the on- resistance, the minimum v gs threshold voltage and the input capacitance. the hv9150 gate driver is designed to drive a maximum of 300pf capacitive load. so, the maximum input capacitance of the external mosfet should be less than 300pf. the minimum breakdown voltage must be larger than the required dc/dc converter output voltage. if the breakdown voltage is too low, the output will never reach the required voltage output. a mosfet with high on-resistance will limit the peak current charging the inductor. the user can use a simple rl charging circuit equation to determine its fnal charging current. it is recommended that the calculated value of i l is within 95% of the i peak calculated in step 2. an on-resistance of less than 1 is usually a good starting point. if the fnal circuit is short on the output current capability, there are a few ways to boost the output. the user can do any or all of the following to improve the output: (1) increase the duty cycle (2) decrease the f gate (3) use a mosfet with lower on-resistance. v o = v i 1 + 1 + 4d 2 2 k ( ( i l = v i 1 - ex p - d r on r on f ga te l ( ( hv9150 supertex inc. www .supertex.com doc.# dsfp-hv9150 nr120213
9 typical application circuits charge pump (cp) mode linear regulator (ldo) mode ccp2 0.22f r freq v out 6.0 - 500v v in 2.7 - 4.5v gnd r 1 r 2 l ct delay osc vref 3x charge pump converter ldo ccp1 0.22f vdd 0.22f vll 1.0f cp_en - + v ll v ll v ll v dd ga te ext_ref fb_rtn fb en freq_adj vcontrol 0v/3.3v v dd ldo mode cp mode ccp2 r freq v out 15 - 500v v in 5.0 - 12 v gnd r 1 r 2 l ct delay osc vref 3x charge pump converter ldo ccp1 vdd vll cp_en - + v ll v ll v ll v dd ga te ext_ref fb_rtn fb en freq_adj vcontrol 0v/3.3v v dd 1.0f ldo mode cp mode hv9150 supertex inc. www .supertex.com doc.# dsfp-hv9150 nr120213
10 typical performance characteristics 35 30 25 20 15 10 5 0 0 50 100 15 0 200 250 300 350 ti me (ns) load capacitance (pf) gate driver rise ti me (t r ) and fall ti me (t f ) vs load capacitance at 25 o c rise time t r , v dd = 11 v (cp mode) fall time t f , v dd = 11 v (cp mode) rise time t r , v dd = 5v (ldo mode) fall time t f , v dd = 5v (ldo mode) 1000 100 10 10 100 1000 frequency (khz) r freq (k ) ga te dr iv er sw it chi ng fr equency vs r freq (v in = 3. 3v at 25 o c) hv9150 supertex inc. www .supertex.com doc.# dsfp-hv9150 nr120213
11 typical performance characteristics (cont.) 100 10 1.0 0.1 10 100 1000 10000 ecrcekvcpeg"*?h+" fgnc{"*ou+ e v "ecrcekvqt"x cnwg"xu"fgnc{"v kog"cv"47 q e 12.0 11 .0 10.0 9.0 8.0 7.0 6.0 407""""""""""""""""""""""""""""""""""""""""""""502""""""""""""""""""""""""""""""""""""""""""""""507"""""""""""""""""""""""""""" """"""""""""""""""602"""""""""""""""""""""""""""""""""""""""""""""607"""""""""""""""""""""""""""""""""""""""""""""702 ejctig"rwor"qwvrwv"x qnvcig"x ff "*x+ kprwv"x qnvcig"x nn "*x+ ejctig"rwor"qwvrwv"x qnvcig"xu"kprwv"x qnvcig"cv"47 q e cl=100pf cl=220pf cl=330pf hv9150 supertex inc. www .supertex.com doc.# dsfp-hv9150 nr120213
12 typical performance characteristics (cont.) 12 11 10 9.0 8.0 7.0 6.0 5.0 0 50 100 150 200 250 300 35 0 output v oltage v dd (v) loa d ca pa ci tan ce (pf) charge pump output v oltage vs load capacitance at 25 o c (f ga te = 100khz, c cp1 = c cp2 = 0.22f , c vdd = 1.0f) v ll = 4.5v v ll = 3.6v v ll = 3.3v v ll = 2.7v 101 100 99 98 97 96 2.0 3.0 4.0 5.0 6.0 7.0 8. 0 9.0 10 11 12 13 14 frequency (khz) v ll input v oltage (v) ldo mode cp mode gate driver switching frequency vs v ll input v oltage (gate output load capacitance = 330pf , r freq = 255k @ 25 o c) hv9150 supertex inc. www .supertex.com doc.# dsfp-hv9150 nr120213
13 typical performance characteristics (cont.) 100 90 80 70 60 50 40 30 20 10 0 x eq pv tq n "h tq o" oc z" vq "o kp x eq pv tq n "h tq o" ok p" vq "o cz rg t egp vc ig "q h" x nn fw v{ "e {eng "u gn gevk qp"j {uv gt guku "c v" xe qp vt qn "r kp "c v" "4 7 q e :4' 84' 64' 44' 9:' 7:' 5:' 3:' :9'"fwv{"e{eng 97'"fwv{"e{eng 84'"fwv{"e{eng 72'"fwv{"e{eng 2'"fwv{"e{eng :9'"fwv{"e{eng 97'"fwv{"e{eng 84'"fwv{"e{eng 72'"fwv{"e{eng 2'"fwv{"e{eng v in = 4.5v v in = 2.7v vcp noise hv9150 supertex inc. www .supertex.com doc.# dsfp-hv9150 nr120213
14 switching waveforms enabling to use the external voltage reference delay time at fb_rtn initial power up x qwv "*gzvatgh+ x qwv "*kpvatgh+ 2x x kj x kn xqwv gp t dela y 2x 2x x kj x kn xqwv hdatvp gp pin description pin # function description 1 vll input supply voltage 2 gnd ground connection 3 en enable 4 cp_en charge pump/ldo enable input 5 vcontrol duty cycle adjustment voltage control input 6 freq_adj frequency adjustment 7 ext_ref external reference voltage input 8 ct timing capacitor 9 fb feedback input voltage 10 fb_rtn feedback return 11 gate gate control output 12 vdd charge pump output voltage 13 ccp2+ charge pump storage capacitor #2 plus terminal 14 ccp2- charge pump storage capacitor #2 minus terminal 15 ccp1+ charge pump storage capacitor #1 plus terminal 16 ccp1- charge pump storage capacitor #1 minus terminal center pad substrate connection (at ground potential) hv9150 supertex inc. www .supertex.com doc.# dsfp-hv9150 nr120213
15 16-lead qfn package outline (k6) 3.00x3.00mm body, 1.00mm height (max), 0.50mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.18 2.85* 1.50 2.85* 1.50 0.50 bsc 0.20 ? 0.00 0 o nom 0.90 0.02 0.25 3.00 1.65 3.00 1.65 0.30 ? - - max 1.00 0.05 0.30 3.15* 1.80 3.15* 1.80 0.45 0.15 14 o jedec registration mo-220, variation veed-4, issue k, june 2006. * this dimension is not specifed in the jedec drawing. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc.#: dspd-16qfnk63x3p050, version a092909. seating plane t op vi ew side v iew bottom v iew a a1 d e d2 e b e2 a3 l l1 v iew b vi ew b 1 note 3 note 2 note 1 (index area d/2 x e/2) note 1 (index area d/2 x e/2) 16 1 16 notes: 1. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. 2. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. 3. the inner tip of the lead may be either rounded or square. supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com hv9150 (the package drawing(s) in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv9150 nr120213

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